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GS84118T/B-166/150/133/100
TQFP, BGA Commercial Temp Industrial Temp
Features
* 3.3 V +10%/-5% core power supply, 2.5 V or 3.3 V I/O supply * Intergrated data comparator for Tag RAM application * FT mode pin for flow through or pipeline operation * LBO pin for Linear or Interleave (PentiumTM and X86) Burst mode * Synchronous address, data I/O, and control inputs * Synchronous Data Enable (DE) * Asynchronous Output Enable (OE) * Asynchronous Match Output Enable (MOE) * Byte Write (BWE) and Global Write (GW) operation * Three chip enable signals for easy depth expansion * Internal self-timed write cycle * JTAG Test mode conforms to IEEE standard 1149.1 * JEDEC-standard 100-lead TQFP package and 119-BGA: T:TQFP or B: BGA -166 Pipeline 3-1-1-1 Flow Through 2-1-1-1 tcycle tKQ IDD tKQ tcycle IDD 6.0 ns 3.5 ns 310 mA 8.5 ns 10 ns 190 mA -150 6.6 ns 3.8 ns 275 mA 10 ns 10 ns 190 mA -133 7.5 ns 4.0 ns 250 mA 11 ns 15 ns 140 mA -100 10 ns 4.5 ns 190 mA 12 ns 15 ns 140 mA
256K x 18 Sync Cache Tag
166 MHz-100 MHz 8.5 ns-12 ns 3.3 V VDD 3.3 V and 2.5 V I/O
Output registers and the Match output register are provided and controlled by the FT mode pin (Pin 14). Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation. Flow Through mode reduces latency. Byte write operation is performed by using Byte Write Enable (BWE) input combined with two individual byte write signals BW1-2. In addition, Global Write (GW) is available for writing all bytes at one time. Compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. The comparator compares the read data with the registered input data and a match signal is generated. The match output can be either in Pipeline or Flow Through modes controlled by the FT signal. Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK). Memory data is retained during Standby mode. JTAG boundary scan interface is provided using IEEE standard 1149.1 protocol. Four pins--Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS)--are used to perform JTAG function. The GS84118 operates on a 3.3 V power supply and all inputs/ outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output (VDDQ) pins are used to allow both 3.3 V or 2.5 V IO interface.
Functional Description
The GS84118 is a 256K x 18 high performance synchronous SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with PentiumTM and other high performance CPUs. It is designed to be used as a Cache Tag SRAM, as well as data SRAM. Addresses, data IOs, match output, chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are synchronous and are controlled by a positive-edge-triggered clock (CLK). Output Enable (OE), Match Output Enable, and power down control (ZZ) are asynchronous. Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst addresses are generated internally and are controlled by ADV. The burst sequence is either interleave order (PentiumTM or x86) or linear order, and is controlled by LBO. Rev: 1.05 7/2001 1/30
* Pentium is a trademark of Intel Corp.
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS84118T/B-166/150/130/100
Pin Configuration
NC NC NC VDDQ VSS NC NC DQ9 DQ10 VSS VDDQ DQ11 DQ12 FT VDD NC VSS DQ13 DQ14 VDDQ VSS DQ15 DQ16 DQP2 NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 CE1 CE2 NC NC BW2 BW1 CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9
A10 NC NC VDDQ VSS NC DQP1 DQ8 DQ7 VSS VDDQ DQ6 DQ5 VSS NC VDD ZZ DQ4 DQ3 VDDQ VSS DQ2 DQ1 NC NC VSS VDDQ
MATCH
DE MOE
Rev: 1.05 7/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 TMS TDI VSS VDD TDO TCK A15 A14 A13 A12 A11 A16 A17 2/30 (c) 1999, Giga Semiconductor, Inc.
LBO A5 A4
GS84118T/B-166/150/130/100
84118 PadOut
119-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQB1 NC VDDQ NC DQB4 VDDQ NC DQB6 VDDQ DQB8 NC NC NC VDDQ
2
A6 E2 A5 NC DQB2 NC DQB3 NC VDD DQB5 NC DQB7 NC DQP2 A2 A10 TMS
3
A7 A4 A3 VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A11 TDI
4
ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD NC NC
5
A8 A15 A14 VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A12 TDO
6
A9 E3 A16 DQP1 NC DQA7 NC DQA5 VDD NC DQA3 MATCH DQA2 MOE A13 A17 TCK
7
VDDQ NC NC NC DQA8 VDDQ DQA6 NC VDDQ DQA4 NC VDDQ DE DQA1 NC ZZ VDDQ
Rev: 1.05 7/2001
3/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
TQFP Pin Description Pin Location
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 89 87 93 94 88 92, 97, 98 86 83 84, 85 58, 59, 62 ,63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23 74, 24 53 51 52 64 14 31 38 39 42 43 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 1, 2, 3, 6, 7, 16, 25, 28, 29, 30,56, 57, 66, 75, 78, 79, 95, 96
Symbol
A0-A17 CLK BWE BW1 BW2 GW CE1,CE2, CE3 OE ADV ADSP, ADSC DQ1-DQ16 DQP1-DQP2 MATCH MOE DE ZZ FT LBO TMS TDI TDO TCK VDD VSS VDDQ NC
Description
Address Input Signals--Inputs are registered and must meet setup and hold times, as specified on page 11. Clock Input Signal Byte Write Enable Signal--The byte write enable signal needs to be combined with one of the four byte write signals for a write operation to occur. Byte Write signal for data outputs 1 thru 8 Byte Write signal for data outputs 9 thru 16 Global Write Enable Chip Enables Output Enable Burst address advance Address status signals Data Input and Output pins Parity Input and Output pins Match Output Match Output Enable Data Enable--Data input registers are updated only when DE is active. Power down control--Application of ZZ will result in a low standby power consumption. Flow Through or Pipeline mode Linear Order Burst mode Test Mode Select Test Data In Test Data Out Test Clock 3.3 V power supply Ground 2.5 V/3.3 V output power supply No Connect
Rev: 1.05 7/2001
4/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
PBGA Pin Description Pin Location
P4, N4, R2, C3, B3, C2, A2, A3, A5, A6, T6, C5, R6, T5, T2, T3, B5, C6 K4 M4 L5 G3 H4 E4, B2, B6 F4 G4 A4, B4 P7, N6, L6, K7, H6, G7, F6, E7, D1, E2, G2, H1, K2, L1, M2, N1 D6, P2 M6 P6 N7 T7 R5 R3 U2 U3 U5 U4 C4, J2, J4, J6, R4 D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5, N3, N5, P3, P5 A1, A7, F1, F7, J1, J7, M1, M7, U1, U7 B1, B7, C1, C7, D2, D4, D7, E1, E6, F2, G1, G5, G6, H2, H7, J3, J5, K1, K6, L2, L3, L4, L7, N2, P1, RR1, R7, T1, T4, U6
Symbol
A0-A17 CLK BWE BW1 BW2 GW CE1,CE2, CE3 OE ADV ADSP, ADSC DQ1-DQ16 DQP1-DQP2 MATCH MOE DE ZZ FT LBO TMS TDI TDO TCK VDD VSS VDDQ NC
Description
Address Input Signals--Inputs are registered and must meet setup and hold times, as specified on page 11. Clock Input Signal Byte Write Enable Signal--The byte write enable signal needs to be combined with one of the four byte write signals for a write operation to occur. Byte Write signal for data outputs 1 thru 8 Byte Write signal for data outputs 9 thru 16 Global Write Enable Chip Enables Output Enable Burst address advance Address status signals Data Input and Output pins Parity Input and Output pins Match Output Match Output Enable Data Enable--Data input registers are updated only when DE is active. Power down control--Application of ZZ will result in a low standby power consumption. Flow Through or Pipeline mode Linear Order Burst mode Test Mode Select Test Data In Test Data Out Test Clock 3.3 V power supply Ground 2.5 V/3.3 V output power supply No Connect
Rev: 1.05 7/2001
5/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Functional Block Diagram
18 A0-17
REGISTER
D
Q
A0 A1
A0 D0 D1 BINARY COUNTER Q0 Q1 A1 18 A
Load LBO ADV CLK ADSC ADSP Q
256K X 18
Memory Array
D
GW BWE BW1 Register D Q BW2 D Q D
Register Register Register
Register D Q
18 2
18
Q
Q
D
DE Register D Q
CE1 CE2 CE3 ZZ FT OE MOE A, DQ, Control Powerdown Control
Register D Q
Register D Q
18 54 Boundary Scan Registers Bypass Reg ID Reg. Instruction Reg. TDO DQ1-16 DQP1-2 Match
TDI
TMS TCK
TAP Controller
Rev: 1.05 7/2001
6/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Mode Pin Function LBO
L H or NC
Function
Linear Burst Interleaved Burst
FT
L H or NC
Function
Flow Through Pipeline
Power Down Control ZZ
L or NC H
Function
Active Standby, IDD = ISB
Note: There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
Byte Write Function Function
Read Read Write all bytes Write all bytes Write byte 1 Write byte 2 Note: H = logic high, L = logic low, NC = no connect
GW
H H L H H H
BWE
H L X L L L
BW1
X H X L L H
BW2
X H X L H L
Rev: 1.05 7/2001
7/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Synchronous Truth Table
Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used none none none none none external external external external external next next next next next next current current current current current current CE1 H L L L L L L L L L X X H H X H X X H H X H CE2 X L X L X H H H H H X X X X X X X X X X X X CE3 X X H X H L L L L L X X X X X X X X X X X X ADSP X L L H H L L H H H H H X X H X H H X X H X ADSC L X X L L X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X L L L L L L H H H H H H Write X X X X X X X H H L H H H H L L H H H H L L OE CLK X X X X X L H L H X L H L H X X L H L H X X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z Q High-Z Q High-Z D Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Notes: 1. X means "don't care," H means "logic high," L means "logic low." 2. 3. 4. 5. 6. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail. All inputs, except OE, must meet setup and hold on rising edge of CLK. Suspending busrt generates a wait cycle. ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK). A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle. Refer to page 12 for the Write timing diagram.
Rev: 1.05 7/2001
8/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Truth Table For Read/Write/Compare/Fill Write Operation CE
Read Write Compare Fill Write Match Deselect Deselect L L L L H H
Write
H L H L X X
DE
X L L H X X
MOE
X X L X L H
OE
L H H X X X
Match
-- -- Data Out -- High High Z
DQ
Q D D X High Z High Z
Notes: 1. X means "don't care," H means "logic high," L means "logic low." 2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail. 3. CE is defined as CE1=L, CE2=H and CE3=L 4. All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.
Absolute Maximum Ratings (Voltage reference to VSS = 0 V) Symbol
VDD VDDQ VCLK Vin Vout Iout PD TOPR TSTG
Description
Supply Voltage Output Supply Voltage CLK Input Voltage Input Voltage Output Voltage Output Current per I/O Power Dissipation Operating Temperature Storage Temperature
Commerical
-0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDD + 0.5 ( 4.6 V max. ) -0.5 to VDD + 0.5 ( 4.6 V max. ) +/-20 1.5 0 to 70 -55 to 125
Unit
V V V V V mA W
oC o
C
Note: Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the performance and reliability of this component.
Rev: 1.05 7/2001
9/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP)
Notes:
Layer Board
single four --
Symbol
RJA RJA RJC
TQFP max
32 20 7
PBGA max
28 18 4
Unit
C/W C/W C/W
Notes
1,2 1,2 3
1. 2. 3.
Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. SCMI G-38-87. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
AC Test Conditions
(VDD = 3.135 V-3.6 V, TA = 0-70C)
Output load 1 DQ
Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. 2. 3. 4. Include scope and jig capacitance.
Conditions
VIH = 2.3 V VIL = 0.2 V TR = 1 V/ns 1.25 V 1.25 V Fig. 1& 2 DQ 5pF1 FIG. 2 FIG. 1 Output load 2 2.5 V 225W 225W 50W VT = 1.25 V 30pF1
Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. Output load 2 for tLZ, tHZ, tOLZ and tOHZ. Device is deselected as defined by the Truth Table.
Rev: 1.05 7/2001
10/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
DC Characteristics and Supply Currents (Voltage reference to VSS = 0 V)
(VDD = 3.135 V-3.6 V, Ta = 0-70C for Commercial Temperature Offering)
Parameter
Input Leakage Current (except ZZ, FT, LBO pins) ZZ Input Current Mode Input Current (FT & LBO pins) Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IinZZ IinM Iol VOH VOH VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -4 mA, VDDQ = 2.375 V IOH = -4 mA, VDDQ = 3.135 V IOL = +4 mA
Min
-1 uA -1 uA -1 uA -30 0uA -1 uA -1 uA 1.7 V 2.4 V
Max
1 uA 1 uA 300 uA 1 uA 1 uA 1 uA
0.4 V
Rev: 1.05 7/2001
11/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Operating Currents
-166 Parameter Test Conditions Symbol 0 to 70C 310 190 30 30 110 80 -40 to +85C 320 200 40 40 120 90 -150 0 to 70C 275 190 30 30 105 80 -40 to +85C 285 200 40 40 115 90 -133 0 to 70C 250 140 30 30 100 65 -40 to +85C 260 150 40 40 110 75 -100 0 to 70C 190 140 30 30 80 65 -40 Unit to +85C 200 150 40 40 90 75 mA mA mA mA mA mA
Operating Current
Device Selected; All other inputs VIH Or VIL Output open
IDD Pipeline IDD Flow Through ISB Pipeline ISB Flow Through IDD Pipeline IDD Flow Through
Standby Current
ZZ VDD - 0.2 V
Deselect Supply Current
Device Deselected; All other inputs VIH OR VIL
Rev: 1.05 7/2001
12/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
AC Electrical Characteristics
Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Pipeline Clock to Match Valid Clock to Match Invalid Clock to Match in Low-Z Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Flow-Thru Clock to Match Valid Clock to Match Invalid Clock to Match in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z OE to Output Valid OE to output in Low-Z OE to output in High-Z MOE to Match Valid MOE to Match in Low-Z MOE to Match in High-Z Symbol tKC tKQ tKQX tLZ1 tKM tKMX tMLZ1 tKC tKQ tKQX tLZ1 tKM tKMX tMLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tMOE tMOLZ1 tMOHZ1 -166 Min 6.0 -- 1.5 1.5 -- 1.5 1.5 10.0 -- 3.0 3.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- -- 0 -- Max -- 3.5 -- -- 3.5 -- -- -- 8.5 -- -- 8.5 -- -- -- -- 3.5 3.5 -- 3.5 3.5 -- 3.5 -150 Min 6.7 -- 1.5 1.5 -- 1.5 1.5 10.0 -- 3.0 3.0 -- 3.0 3.0 1.5 1.7 1.5 -- 0 -- -- 0 -- Max -- 3.8 -- -- 3.8 -- -- -- 10.0 -- -- 10.0 -- -- -- -- 3.8 3.8 -- 3.8 3.8 -- 3.8 -133 Min 7.5 -- 1.5 1.5 -- 1.5 1.5 15.0 -- 3.0 3.0 -- 3.0 3.0 1.7 1.9 1.5 -- 0 -- -- 0 -- Max -- 4 -- -- 4 -- -- -- 11.0 -- -- 11.0 -- -- -- -- 4 4 -- 4 4 -- 4 -100 Min 10 -- 1.5 1.5 -- 1.5 1.5 15.0 -- 3.0 3.0 -- 3.0 3.0 2 2.2 1.5 -- 0 -- -- 0 -- Max -- 4.5 -- -- 4.5 -- -- -- 12.0 -- -- 12.0 -- -- -- -- 5 5 -- 5 5 -- 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Rev: 1.05 7/2001
13/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
AC Electrical Characteristics
Parameter Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tS tH tZZS2 tZZH2 tZZR -166 Min 1.5 0.5 5 1 20 Max -- -- -- -- -- -150 Min 1.5 0.5 5 1 20 Max -- -- -- -- -- -133 Min 2.0 0.5 5 1 20 Max -- -- -- -- -- -100 Min 2.0 0.5 5 1 20 Max -- -- -- -- -- Unit ns ns ns ns ns
Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.05 7/2001
14/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Write Cycle Timing
Single Write
Burst Write
Write
Deselected
CLK
tS tH
tKH tKL
tKC
ADSP is blocked by CE1 inactive
ADSP
tS tH ADSC initiated write
ADSC
tS tH
ADV A0-A17 GW
tS tH
WR1
ADV must be inactive for ADSP Write
WR2 WR3
tS tH
tS tH
BWE
tS tH
BW1- BW2 CE1
WR1 WR1
WR2 WR2
WR3 WR3
tS tH tS tH
CE1 masks ADSP
Deselected with CE2
CE2
tS tH CE2 and CE3 only sampled with ADSP or ADSC
CE3 OE DQ1-16 DQP1-2 DE
Hi-Z
tS tH
D1a
Write specified byte for 2a and all bytes for 2b, 2c& 2d
D2a D2b D2c D2d D3a
tS tH
Rev: 1.05 7/2001
15/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Flow Through--Read Cycle Timing
Single Read
Single Read
CLK ADSP ADSC ADV A0-A17 GW
tS tH
tKH tS tH
tKC
tKL
ADSP is blocked by CE1 inactive
ADSC initiated read
tS tH
Suspend Burst
Suspend Burst
tS tH RD1 tS RD2 RD3 tH
tS
tH
BWE BW1- BW2 CE1
tS tH CE2 and CE3 only sampled with ADSP or ADSC Deselected with CE2
tS tH
CE1 masks ADSP
CE2
tS tH
CE3
tOE
OE DQ1-16 DQP1-2
Hi-Z tOLZ tLZ tKQ
tOHZ Q1a
tKQX Q2a Q2b Q2c Q2d Q3a
tKQX
tHZ
Rev: 1.05 7/2001
16/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Flow Through--Read/Write Cycle Timing
Single Read
Single Write
Burst Read
CLK
tS tH tKH tKL
tKC
ADSP is blocked by CE1 inactive ADSC initiated read
ADSP
tS tH
ADSC
tS tH
ADV
tS tH
A0-A17 GW
RD1
WR1
RD2
tS tH
tS
tH
BWE BW1- BW2 CE1
tS tH CE2 and CE3 only sampled with ADSP and ADSC tS tH
WR1
tS tH
CE1 masks ADSP
CE2
tS tH Deselected with CE3 tOE tOHZ
CE3 OE DQ1-16 DQP1-2 DE
Hi-Z tKQ Q1a tS tH D1a tS tH Q2a Q2b Q2c Q2d Q2a
Burst wrap around to its initial state
Rev: 1.05 7/2001
17/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Pipeline--Read Cycle Timing
Single Read
Burst Read tKH tS tH tKL
CLK ADSP ADSC ADV A0-A17 GW
tS tH
tKC
ADSP is blocked by CE1 inactive
ADSC initiated read
tS tH
Suspend Burst
tS tH RD1 tS RD2 RD3 tH
tS
tH
BWE BW1- BW4 CE1
tS tH CE2 and CE3 only sampled with ADSP or ADSC Deselected with CE2
tS tH
CE1 masks ADSP
CE2
tS tH
CE3 OE DQ1-16 DQP1-2
Hi-Z tOLZ
tOE tOHZ Q1a tLZ tKQ tKQX Q2b Q2c Q2d Q3a tHZ
tKQX Q2a
Rev: 1.05 7/2001
18/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Pipeline--Read/Write Cycle Timing
Single Write
tKC
Single Read
Burst Read
CLK
tS tH tKH tKL tS tH
ADSP is blocked by CE1 inactive ADSC initiated read
ADSP ADSC
tS tH
ADV
tS tH
A0-A17 GW
RD1
WR1
RD2
tS tH
tS
tH
BWE BW1- BW4 CE1
tS tH CE2 and CE3 only sampled with ADSP and ADSC tS tH WR1 tS tH CE1 masks ADSP
CE2
tS tH Deselected with CE3 tOE tOHZ
CE3 OE DQ1-16 DQP1-2 DE
Hi-Z tKQ
tS tH Q1a D1a tS tH Q2a Q2b Q2c Q2d
Rev: 1.05 7/2001
19/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Flow Through--Compare/Fill Write Cycle Timing
CLK CE
(1)
tS
tH
W(2) OE A0-A17 DQ1-16 DQP1-2 DE MOE MATCH tKM tMOE tMLZ tKMX tKM tKM
Match high when chip deselected
A A
B B
B
Hit
Miss
Fill Write
Notes: 1. CE = L is defined as CE1=L, CE2=H and CE3=L 2. W = L is the Asertive function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
Rev: 1.05 7/2001
20/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Pipeline--Compare/Fill Write Cycle Timing
CLK CE
(1)
tS
tH
W(2) OE A0-A17 DQ1-16 DQP1-2 DE tKM MOE tMLZ MATCH Hit Miss Fill Write tMOE tKMX tKM tKM
Match high when chip deselected
A A
B B
B
Notes: 1. CE = L is defined as CE1=L, CE2=H and CE3=L 2. W = L is the Asertive function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
Rev: 1.05 7/2001
21/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
ZZ Timing
tS tH
tKC
tKH tKL
ADSP ADSC ZZ
tZZS
~~~~~~ ~~~~~~~ ~
CLK
tZZR
Snooze tZZH
Rev: 1.05 7/2001
22/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Test Mode Description
Functional Description
The GS84118 provides JTAG boundary scan interface using IEEE standard 1149.1 protocol. The Test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAM, other components and the Printed Circuit Board.
Test Access Port (TAP)
Four pins (as defined in Pin Description Tables) are used to performed JTAG functions. TDI input is used to scan test data serially into one of three registers (Instruction Register, Boundary Scan Register and Bypass Register). TDO is the output pin to serially output scan test data. The TDI sends the data into the LSB of the selected register and the MSB of that register feeds the data to TDO. TMS input pin controls the state transition of 16 state TAP controllers, as specified in IEEE standard 1149.1. Inputs on TDI and TMS are registered on the rising edge of TCK clock, and the output data on TDO is presented on the falling edge of TCK. The TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift -DR state.
TAP Controller
Sixteen state controllers are implemented as specified in IEEE standard 1149.1. The controller enters the Reset state either through * Power up or * Apply logic 1 on TMS input pin on 5 consecutive rising edges.
1 Test Logic Reset 0 0 Run Test Idle 1
Tap Controller State Diagram
Select DR 0 1 Capture DR 0
1
Select IR 0 1 Capture IR 0
1
0 Shift DR 1 1 Exit1 DR 0 0 Pause DR 1 Exit2 DR 1 Update DR 0 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 1 Shift IR 1 Exit1 IR 0
0
0
0
1
Rev: 1.05 7/2001
23/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Instruction Register (3 Bits)
The JTAG Instruction register is consisted of shift register stage and parallel output latch. The register is 3 bits wide and is encoded as follow:
Octal
0 1 2 3 4 5 6 7
MSB
0 0 0 0 1 1 1 1
--
0 0 1 1 0 0 1 1
LSB
0 1 0 1 0 1 0 1
Instruction
Bypass IDCODE--Read device ID Sample-Z--Sample Inputs and tri-state DQs, Match Bypass Sample--Sample Inputs Private--Manufacturer use only Bypass Bypass
Bypass Register (1 Bit)
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serially path between TDI and TDO.
ID Register (32 Bits)
The ID Register are 32 bits wide and are listed as follow: Header GSI ID (89 decimal in bank 2) Part Number Revision Number ID[0] ID[7:1] ID[11:8] ID[27:12] ID[31:28] 1 101 1001 0001 0000 0000 0000 0000 xxxx
Rev: 1.05 7/2001
24/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Boundary Scan Register (54 Bits)
The Boundary Scan Register are 54 bits wide and are listed as follow: DQx, Match Address GW, BWE, BW1-2, DE CE1, CE2, CE3 OE, MOE ADSP, ADSC, ADV ZZ, FT, LBO CLK Total 19 18 5 3 2 3 3 1 54
Scan Order (Order by exit sequence) Order
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Signal
A15 A14 A13 A12 A11 A16 A17 MOE DE MATCH DQ1 DQ2 DQ3 DQ4 ZZ DQ5 DQ6 DQ7 DQ8 DQP1 A10 A9 A8 ADV ADSP ADSC OE
TQFP
44 45 46 47 48 49 50 51 52 53 58 59 62 63 64 68 69 72 73 74 80 81 82 83 84 85 86
BGA
3T 2T 5T 6R 5C 5B 6C 6P 7N 6M 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F
Order
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
Signal
BWE GW CLK CE3 BW1 BW2 CE2 CE1 A7 A6 DQ9 DQ10 DQ11 DQ12 FT DQ13 DQ14 DQ15 DQ16 DQP2 LBO A5 A4 A3 A2 A1 A0
TQFP
87 88 89 92 93 94 97 98 99 100 8 9 12 13 14 18 19 22 23 24 31 32 33 34 35 36 37
BGA
4M 4H 4K 6B 5L 3G 2B 4E 3A 2A 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3B 3C 2R 4N 4P
Rev: 1.05 7/2001
25/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Test Mode AC Electrical Characteristics Parameter
TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time
Symbol
tTKC tTKQ tTKH tTKL tTS tTH
Min
20 -- 10 10 5 5
Max
-- 10 -- -- -- --
Unit
ns ns ns ns ns ns
Test Mode Timing Diagram tTKH
TCK
tTKL tTS tTH
tTKC
TMS
TDI
TDO
tTKQ
Rev: 1.05 7/2001
26/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Package Dimensions--100-Pin TQFP L L1 c Pin 1
e
D1
D
b
A1 Y
A2
E1 E Min.
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 0.45 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.10 0 7 0.75
Symbol
A1 A2 B C D D1 E E1 E L L1 Y Q Notes:
1. 2.
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Nom.
0.10 1.40 0.30
Max
0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1
All dimesnions are in millimeters (mm). Package wideth and length do not include mold protrusion.
Rev: 1.05 7/2001
27/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Package Dimesions - 119 Pin PBGA
Pin 1 Corner
A
7654321
G
P
B
S
D
A B C D E F G H J K L M N P R T U
N
Top View
R Bottom View
Package Dimesions - 119 Pin PBGA
T
Symbo l
A B C D E F G K N P R S T Unit: mm
Description
Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Cut-out Package Width Foot Length Width of package between balls Length of package between balls Variance of Ball Height
Min Nom Ma . . x
13.8 21.8 0.60 0.50 0.75 0.60 1.46 1.27 0.80 0.90 12.00 19.50 7.62 20.32 0.15 1.00 14.0 22.0 14.2 22.2 2.40 0.90 0.70 1.70
F
Side View
BPR 1999.05.18
Rev: 1.05 7/2001
C
E
K
28/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Ordering Information Org
256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18
Part Number1
GS84118T-166 GS84118T-150 GS84118T-133 GS84118T-100 GS84118T-166I GS84118T-150I GS84118T-133I GS84118T-100I GS84118B-166 GS84118B-150 GS84118B-133 GS84118B-100 GS84118B-166I GS84118B-150I GS84118I-133I GS84118B-100I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP BGA BGA BGA BGA BGA BGA BGA BGA
Speed2 (MHz/ns)
166/8.5 150/10 133/11 100/12 166/8.5 150/10 133/11 100/12 166/8.5 150/10 133/11 100/12 166/8.5 150/10 133/11 100/12
TA
3
Status
C C C C I I C I C C C C I I C I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS84032T-7.5T. 2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline / Flow through mode selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.05 7/2001
29/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
4Mb Synchronous Tag RAM Datasheet Revision History Rev. Code: Old;New
GS84118-2000207; 84118_r1_01 84118_r1_02; 84118_r1_03
Types of Changes Page /Revisions;Reason Format or Content
Content * Updated BGA Pin Description to meet JEDEC standard * Updated format to comply with Technical Publications standards * Corrected typo in TQFP Package Description table on page 27 * Updated Pinout on page 3 * Updated Pin Description tables for TQFP and PBGA * Added overbar to all references of BWE, BW1, BW2, GW, CE1, CE3, OE, ADV, ADSP, ADSC, MOE, DE, FT, and LBO * Removed VDD note from AC Electrical Characteristics table * Imported up-to-date Package Drawing for 119 PBGA * Reordered pin location listings in pin description tables on pages 4 and 5 * Removed Global Write reference from BWE description in pin description tables * Removed BWE reference from GW description in pin description tables * Placed overbars on Write references in Synchronous Truth Table
Content/Format
84118_r1_03; 84118_r1_04
Content
84118_r1_04; 84118_r1_05
Content
Rev: 1.05 7/2001
30/30
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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